74HC160 데이터 시트보기 (PDF) - NXP Semiconductors.

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74HC160

Presettable synchronous BCD decade counter; asynchronous reset

NXP Semiconductors. 

Nexperia

74HC160

Presettable synchronous BCD decade counter; asynchronous reset

9,

&(7LQSXW

*1'

92+

7&RXWSXW

92/

90

W3/+





90

W7/+

W3+/





W7+/

DDD

Measurement points are given in Table 8.

Logic levels VOL and VOH are typical output voltage levels that occur with the output load.

Fig 10. The count enable carry input (CET) to terminal count output (TC) propagation delays and output

transition times

9,

05LQSXW



*1'

9,

&3LQSXW



*1'

92+

4Q7&RXWSXW

92/

90

WUHF

W:

W3+/

90

90

PQD

Measurement points are given in Table 8.

Logic levels VOL and VOH are typical output voltage levels that occur with the output load.

Fig 11. The master reset (MR) pulse width, master reset to output (Qn, TC) propagation delays, and the master

reset to clock (CP) recovery times

74HC160

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 27 September 2016

© Nexperia B.V. 2017. All rights reserved

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