PI3L100
3.3V, Wide Bandwidth, Quad
2:1 Mux/DeMux LAN Switch
DSO
Vo 100Ω
100Ω
S1
IA0 2
IA1 3
YA 4
IB0 5
IB1 6
YB 7
GND 8
PI3L100
16 VCC
15 E
14 ID0
13 ID1
12 YD
11 IC0
10 IC1
9 YC
VCC = 3.3V
0.1µF
100Ω
100Ω
Figure 3. Differential Crosstalk Measurement
TRANSMIT 2
PULSE
GENERATOR
TX1
RX1
PI3L100
TX1
RX1
Figure 4b. Loop Back
RECEIVE 2
OFFSET ADJUST
Figure 4a. Full Duplex Transceiver
120Ω
100Ω
Figure 4c. Line Termination
Figure 4d. Line Clamp
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15-0052
5
www.pericom.com 05/18/15