SMS44G 데이터 시트보기 (PDF) - Summit Microelectronics

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SMS44G

Highly Programmble Voltage Supervisory Circuit

Summit Microelectronics 

SMS44

tPWDTO

t0

t0

IRQ#

t0

t0

t0

RESET#

tPLDTO

WLDI

tPRTO

tPLDTO

2047 Fig03 1.0

Figure 3. Watchdog, Longdog and WLDI Timing

t0

t0

t0

A1, A2

A1 and A2 are the address inputs. When addressing the

SMS44 memory or configuration registers the address

inputs distinguish which one of four possible devices

sharing the common bus is being addressed.

SDA

SDA is the serial data input/output pin. It should be tied to

VCC through a pull-up resistor.

SCL

SCL is the serial clock input. It should be tied to VCC

through a pull-up resistor.

IRQ#

RESET#

WLDI

tPRTO

tPLDTO

2047 Fig04 1.0

Figure 4. Watchdog, Longdog and WLDI Timing

2047 2.3 10/23/00

SUMMIT MICROELECTRONICS, Inc.

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