SL23EP08SI-1HT 데이터 시트보기 (PDF) - SpectraLinear Inc

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SL23EP08SI-1HT

Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)

SpectraLinear Inc 

Pin Configuration

SL23EP08

16-Pin SOIC/TSSOP

Pin Description

Pin

Number

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Pin Name

CLKIN

CLKA1

CLKA2

VDD

GND

CLKB1

CLKB2

S2

S1

CLKB3

CLKB4

GND

VDD

CLKA3

CLKA4

FBK

Pin Type

Pin Description

Input

Output

Output

Power

Power

Output

Output

Input

Input

Output

Output

Power

Power

Output

Output

Output

Reference Frequency Clock Input. 5V tolerant input. Weak pull-down

(250kȍ).

Buffered Clock Output, Bank A. Weak pull-down (250kȍ).

Buffered Clock Output, Bank A. Weak pull-down (250kȍ).

3.3V to 2.5V Power Supply.

Power Ground.

Buffered Clock Output, Bank B. Weak pull-down (250kȍ).

Buffered Clock Output, Bank B. Weak pull-down (250kȍ).

Select Input, select pin S2. Weak pull-up (250kȍ).

Select Input, select pin S1. Weak pull-up (250kȍ).

Buffered Clock Output, Bank B. Weak pull-down (250kȍ).

Buffered Clock Output, Bank B. Weak pull-down (250kȍ).

Power Ground.

3.3V to 2.5V Power Supply.

Buffered Clock Output, Bank A. Weak pull-down (250kȍ).

Buffered Clock Output, Bank A. Weak pull-down (250kȍ).

PLL Feedback input.

Rev 1.4, May 28, 2007

Page 2 of 18

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