ADIS16250(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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ADIS16250 Datasheet PDF : 20 Pages
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TIMING SPECIFICATIONS
TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tDATARATE
tDATARATE
tCSHIGH
tCS
tDAV
tDSU
tDHD
tDF
tDR
tSFS
Description
Fast mode2
Normal mode2
Chip select period, fast mode2
Chip select period, normal mode2
Chip select high
Chip select to clock edge
Data output valid after SCLK edge
Data input setup time before SCLK rising edge
Data input hold time after SCLK rising edge
Data output fall time
Data output rise time
CS high after SCLK edge
1 Guaranteed by design; typical specifications are not tested or guaranteed.
2 Based on sample rate selection.
tDATA RATE
CS
SCLK
Figure 2. SPI Chip Select Timing
Min1
0.01
0.01
40
100
1/fSCLK
48.8
24.4
48.8
5
ADIS16250
Typ
Max1
Unit
2.5
MHz
1.0
MHz
μs
μs
ns
100
ns
ns
ns
5
12.5
ns min
5
12.5
ns min
ns typ
CS
SCLK
DOUT
DIN
tCS
1
MSB
W/R
2
3
4
5
6
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A5
A4
A3
A2
15
16
tSFS
DB2
DB1
LSB
D2
D1
LSB
Figure 3. SPI Timing
(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
Rev. 0 | Page 5 of 20
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