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E692AHJ

200 MHz Monolithic Dual Pin Electronics Driver

Semtech Corporation 

EDGE HIGH-PERFORMANCE PRODUCTS

Circuit Description

Introduction

Driver Levels

The driver circuit will force the DOUT output to one of

three states:

1. DVH (driver high voltage level)

2. DVL (driver low voltage level)

3. High Impedance (Hi Z).

Both driver digital control inputs (DHI/DHI*, DRVEN/

DRVEN*) are wide-voltage differential inputs capable of

receiving ECL, TTL, and CMOS signals. Single-ended

operation is achievable by generating the proper

threshold levels for the inverting inputs.

Drive Enable

The drive enable (DRVEN/DRVEN*) inputs control

whether the driver is forcing a voltage or is placed in a

high-impedance state. If DRVEN is more positive than

DRVEN*, the output will force either DVL or DVH,

depending on the driver data inputs. When DRVEN is

more negative than DRVEN*, the output is set to high-

impedance, independent of the driver data inputs.

Driver Data

The driver data inputs (DHI/DHI*) determine whether

the driver output is high or low. If DHI is more positive

than DHI*, the output will force DVH when the driver is

enabled. If DHI is more negative than DHI*, the output

will force DVL when the driver is enabled.

Table 1 summarizes the functionality of the driver enable

and driver data pins.

DVH and DVL are high input impedance voltage controlled

inputs that establish the driver logical high and low levels

respectively.

DVLCAP / DVHCAP

These two analog nodes are brought out to better

stabilize the high and low driver levels. Much like placing

decoupling capacitors on the DVL and DVH input pins,

the DVLCAP and DVHCAP pins require a fixed .01 µF

chip capacitor (with good high frequency characteristics)

to ground. A tight layout with minimum etch is

recommended.

Driver Bias

The BIAS pin is an analog current input that establishes

a reference current for the driver and influences the

overall speed and power consumption of the chip. The

BIAS input current may be varied from 1.0 mA to 2.0

mA. Ideally, a current source would supply this current.

However, a resistor to a voltage source, typically VCC, is

acceptable.

The BIAS input structure is shown in Figure 1.

VCC

BIAS

REXT

50

DRVEN, DRVEN*

DHI, DHI*

DOUT

DRVEN > DRVEN*

DHI > DHI*

DVH

DRVEN > DRVEN*

DHI < DHI*

DVL

DRVEN < DRVEN*

X

HiZ

VEE

Table 1. DRVEN and DHI Pin Functionality

Figure 1. BIAS Input Structure

 2000 Semtech Corp.

4

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