RTL8196C
Datasheet
2. Features
SOC
CPU Interface (NIC)
Embedded RISC CPU, RLX4181 with
Supports BSD mbuf-like packet structure
16K I-Cache, 8K D-Cache, 16K I-MEM,
with adjustable cluster size (128-byte to
8K D-MEM
2Kbyte) to provide optimum memory
Supports MIPS-1 ISA, MIPS16 ISA
utilization
Clock rate up to 400MHz
Provides the ‘To-CPU reason’ in the
packet header to facilitate packet
Provides a standard 5-signal P1149.1
EJTAG test port
Supports RLX4181 CPU suspend mode
L2 Capabilities
k Five Ethernet MAC integrated switch
with five 10M/100Mbps physical layers
lte and transceivers for IEEE 802.3
10Base-T and 100Base-TX
L Non-blocking wire-speed reception and
a IA transmission and non-head-of-line-
blocking/forwarding
T Internal 512Kbit SRAM for packet
e N N buffering
R E IO Internal 1024 entry 4-way hash L2 look-
T up table
ID RA Supports source and destination MAC
F O address filtering
N P Supports IEEE 802.1x port-based and
R MAC-based Network Access Control
CO CO Complies with
E IEEE 802.3/802.3u/802.1q/802.1d
T Flexible full-duplex 802.3x flow control
Z and optional half-duplex backpressure
forflow control
processing
The NIC DMA supports multiple-
descriptor-ring architecture for QoS
applications (supports 6 RX descriptor
rings and 2 TX descriptor rings)
Peripheral Interfaces
Supports one PCI Express Host with
integrated PHY
Supports one 16550 UART
Supports up to 17 GPIO pins
Supports one-port USB 2.0 host interface
Embedded USB PHY
Memory Interfaces
Flash (NOR Type)
Supports two Flash banks that can be
configured as 8/16-bit bus, 256k/512k
/1M/2M/4M/8M bytes
System supports up to 16Mbyte Flash
memory space
Boot up from NOR Flash is supported
Flash (SPI Type)
Supports 4 channels for SPI Flash
application
Boot up from SPI Flash is supported
MAC learning supports Shared VLAN
System supports up to 32Mbyte Flash
Learning (SVL) and Independent VLAN
memory space
Learning (IVL) modes
IEEE 802.11n AP/Router Network Processor with EEE 2
Track ID: JATR-2265-11 Rev. 0.7