TC58256AFT 데이터 시트보기 (PDF) - Toshiba
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TC58256AFT Datasheet PDF : 33 Pages
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TC58256AFT
Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay
is less than 30 ns, RY/BY signal stays Ready.
tCEH ³ 100 ns
*
*: VIH or VIL
CE
RE
525
526
527 A
A : 0 to 30 ns ® Busy signal is not output.
RY/BY
Busy
tCRY
PROGRAMMING AND ERASING CHARACTERISTICS (Ta = 0° to 70°C, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
tPROG
Programming Time
¾
N
Number of Programming Cycles on Same
¾
Page
tBERASE
Block Erasing Time
¾
(1): Refer to Application Note (12) toward the end of this document.
TYP.
200 to 300
¾
2
MAX
1000
3
10
UNIT
ms
ms
NOTES
(1)
2001-05-30 5/33
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