IDT723612L20PQFI(2002) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT723612L20PQFI
(Rev.:2002)

CMOS SyncBiFIFOTM 64 x 36 x 2

Integrated Device Technology 

IDT723612

CMOS SYNCBiFIFOTM 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

CLKB

CSB

W/RB

MBB

ENB

tCLK

tCLKH

tCLKL

LOW

LOW

LOW

tENS2

tENH2

EFB

B0 - B35

CLKA

FFA

CSA

HIGH

tA

Previous Word in FIFO1 Output Register

tSKEW1(1)

tCLK

tCLKH

tCLKL

1

LOW

FIFO1 Full

Next Word From FIFO1

2

tWFF

tWFF

WRA

MBA

ENA

HIGH

A0 - A35

tENS3

tENH3

tENS2

tENH2

tDS

tDH

To FIFO1

3136 drw12

NOTE:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge

and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.

Figure 9. FFA Flag Timing and First Available Write when FIFO1 is Full

18

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