74F821SCX 데이터 시트보기 (PDF) - Fairchild Semiconductor
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74F821SCX Datasheet PDF : 6 Pages
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Unit Loading/Fan Out
Pin Names
Description
D0–D9
OE
CP
O0–O9
Data Inputs
Output Enable
3-STATE Input
Clock Input
3-STATE Outputs
Functional Description
The 74F821 consists of ten D-type edge-triggered flip-
flops. This device has 3-STATE true outputs for bus sys-
tems organized in a broadside pinning. The buffered Clock
(CP) and buffered Output Enable (OE) are common to all
flip-flops. The flip-flops will store the state of their individual
D inputs that meet the setup and hold times requirements
on the LOW-to-HIGH CP transition. With the OE LOW the
content of the flip-flops are available at the outputs. When
the OE is HIGH, the outputs go to the high impedance
state. Operation of the OE input does not affect the state of
the flip-flops.
Logic Diagram
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
1.0/1.0
20 µA/−0.6 mA
150/40 (33.3) −3.0 mA/24 mA (20 mA)
Function Table
Inputs
Internal Output
OE CP D
Q
O
Function
H H X NC
Z Hold
H
H
H
L
L
L
X
L
H
L
H
NC
H
L
H
L
Z Hold
Z Load
Z Load
L Data Available
H Data Available
L H X NC
NC No Change in Data
L L X NC
NC No Change in Data
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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