LP62E16512-T(2002) 데이터 시트보기 (PDF) - AMIC Technology

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LP62E16512-T
(Rev.:2002)

512K X 16 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

Timing Waveforms (continued)

Write Cycle 3

(Byte Enable Controlled)

Address

CS1

tAS1

CS2

LP62E16512-T Series

tWC

tAW

tCW1 , tCW2

tBW2

tWR3

HB, LB

WE

DATA IN

DATA OUT

tWP

tWHZ4

tDW

tDH

tOW

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP, tBW) of a low CS1 , WE and ( HB and , or LB ) or a high CS2.

3. tWR is measured from the earliest of CS1 or WE or ( HB and , or LB ) going high or CS2 going Low to the end of

the Write cycle.

4. OE level is high or low.

5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (April, 2002, Version 0.0)

10

AMIC Technology, Inc.

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