ISL8484(2006) 데이터 시트보기 (PDF) - Intersil

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ISL8484
(Rev.:2006)

Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch

Intersil 

ISL8484

Thin Dual Flat No-Lead Plastic Package (TDFN)

2X

A

D

0.10 C A

2X

0.10 C B

E

6

INDEX

AREA

TOP VIEW

B

C

SIDE VIEW

SEATING

PLANE

(DATUM B)

D2

D2/2

6

INDEX

AREA

12

(DATUM A)

A

A3

// 0.10 C

0.08 C

78

NX k

E2

E2/2

NX L

8

N N-1

e

(Nd-1)Xe

REF.

BOTTOM VIEW

NX b

5

0.10 M C A B

NX (b)

(A1)

5

SECTION "C-C"

CL

e

CC

L1

9L

TERMINAL TIP

L10.3x3A

10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

MIN NOMINAL MAX

NOTES

A

0.70

0.75

0.80

-

A1

-

-

0.05

-

A3

0.20 REF

-

b

0.20

0.25

0.30

5, 8

D

2.95

3.0

3.05

-

D2

2.25

2.30

2.35

7, 8

E

2.95

3.0

3.05

-

E2

1.45

1.50

1.55

7, 8

e

0.50 BSC

-

k

0.25

-

-

-

L

0.25

0.30

0.35

8

N

10

2

Nd

5

3

NOTES:

Rev. 3 3/06

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

9. Compliant to JEDEC MO-229-WEED-3 except for D2

dimensions.

FOR ODD TERMINAL/SIDE

12

FN6128.2

September 13, 2006

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