ISL8500 데이터 시트보기 (PDF) - Intersil
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ISL8500 Datasheet PDF : 15 Pages
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ISL8500
Typical Performance Curves
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 12V, EN = VDD, L = 10µH,
COUT = 100µF, C2 = 2x22µF, IOUT = 0A to 2A. See “The input supply for the PWM regulator
power stage and the source for the internal linear regulator that provides bias for the IC. Place a
ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 10µF).” on page 6.
(Continued)
1.814
1.813
1.812
12VIN
25VIN
1.811
1.810
1.809
1.808
5VIN
1.807
1.806
0.0
0.5
1.0
1.5
2.0
OUTPUT LOAD (A)
FIGURE 8. VOUT REGULATION vs LOAD, 1.8VOUT
2.506
2.505
2.504
25VIN
2.503
2.502
12VIN
2.501
2.500
2.499
5VIN
2.498
0.0
0.5
1.0
1.5
2.0
OUTPUT LOAD (A)
FIGURE 9. VOUT REGULATION vs LOAD, 2.5VOUT
3.330
3.328
3.326
12VIN
25VIN
3.324
3.322
3.320
3.318
7VIN
3.316
3.314
0.0
0.5
1.0
1.5
2.0
OUTPUT LOAD (A)
FIGURE 10. VOUT REGULATION vs LOAD, 3.3VOUT
4.99
4.98
4.97
25VIN
4.96
4.95
4.94
7VIN
4.93
4.92
12VIN
4.91
0.0
0.5
1.0
1.5
2.0
OUTPUT LOAD (A)
FIGURE 11. VOUT REGULATION vs LOAD, 5VOUT
PHASE 5V/DIV
VOUT RIPPLE
20mV/DIV
IL 0.5A/DIV
FIGURE 12. STEADY STATE OPERATION AT NO LOAD
(5µs/DIV)
8
PHASE 10V/DIV
VOUT RIPPLE
20mV/DIV
IL 1A/DIV
FIGURE 13. STEADY STATE OPERATION AT FULL LOAD
(1µs/DIV)
FN6611.0
December 10, 2007
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