HD6433028F 데이터 시트보기 (PDF) - Renesas Electronics

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HD6433028F

16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Renesas Electronics 

Item

Page

7.4.8 DMAC Bus

230

Cycle

Figure 7.14 Bus

Timing of DMA Transfer

Requested by Low

DREQ Input

Revision (See Manual for Details)

Figure amended

CPU cycle

DMAC cycle

CPU cycle

DMAC cycle

(last transfer cycle)

CPU cycle

T1 T2 T3 Td T1 T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2

φ

DREQ

Address

bus

RD

Source Destination

address address

Source Destination

address address

HWR , LWR

TEND

Figure 7.15 Burst

231

DMA Bus Timing

Figure 7.16 Timing of 232

DMAC Activation by

Falling Edge of DREQ

in Normal Mode

Figure amended

CPU cycle

DMAC cycle

CPU cycle

T1 T2 Td T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2

φ

Address

bus

RD

Source Destination

address address

HWR,

LWR

Figure amended

CPU cycle

DMAC cycle

CPU

cycle DMAC cycle

T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 Td T1 T2

φ

DREQ

Address

bus

RD

HWR , LWR

Minimum 4 states

Next sampling point

Rev. 2.00, 09/03, page viii of xxx

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