IDT71F432L75 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT71F432L75 Datasheet PDF : 5 Pages
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IDT71F432 32Kx32 MCache SYNCHRONOUS PIPELINED CACHE RAM
AC ELECTRICAL CHARACTERISTICS
(VDD = 3.3V +10/-5%, TA = 0 to 70°C)
Symbol
Parameter
Clock Parameters
tF
Clock Frequency
tCYC
tCH(1)
tCL(1)
Clock Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Output Parameters
tCD
Clock High to Valid Data
tCDC
tCLZ(2)
tCHZ(2)
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
tOE
Output Enable Access Time
tOLZ(2)
Output Enable Low to Data Active
tOHZ(2)
Output Enable High to Data High-Z
Set Up and Hold Times
tSxx
Input Setup Time
tHxx
Input Hold Time
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
TIMING WAVEFORMS
CLK
All Inputs
(except OE#)
I/O[31:0]
output
OE#
tCD
tCLZ
tOLZ
tOE
tCYC
tSxx
COMMERCIAL TEMPERATURE RANGE
IDT71F432S75
Min.
Max.
—
75
13.3
—
5
—
5
—
—
6
2
—
0
—
2
15
—
6
0
—
—
6
2.0
—
1.5
—
IDT71F432S66
IDT71F432L66
Min.
Max.
Unit
—
66.7
ns
15
—
ns
6
—
ns
6
—
ns
—
7
ns
2
—
ns
0
—
ns
2
15
ns
—
7
ns
0
ns
—
7
ns
2.5
—
ns
1.5
—
ns
3555 tbl 06
tCH
tHxx
tCDC
tCL
tCHZ
tOHZ
13.1
4
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