HN58S256AT-15 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HN58S256AT-15

256 k EEPROM (32-kword × 8-bit)

Hitachi -> Renesas Electronics 

Block Diagram

VCC

High voltage generator

VSS

OE

CE

Control logic and timing

WE

A0

to

A5

A6

to

A14

Address

buffer and

latch

Y decoder

X decoder

HN58S256A Series

I/O0 to I/O7

I/O buffer

and

input latch

Y gating

Memory array

Data latch

Operation Table

Operation

CE

OE

WE

Read

VIL

VIL

VIH

Standby

VIH

×*2

×

Write

VIL

VIH

VIL

Deselect

VIL

VIH

VIH

Write inhibit

×

×

VIH

×

VIL

×

Data polling

VIL

VIL

VIH

Notes: 1. Refer to the recommended DC operating condition.

2. × = Don’t care

I/O

Dout

High-Z

Din

High-Z

—

—

Data out (I/O7)

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