IDT7MP4045S20Z 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7MP4045S20Z

256K x 32 CMOS STATIC RAM MODULE

Integrated Device Technology 

IDT7MP4045/7MP4145

256K x 32 CMOS STATIC RAM MODULE

TIMING WAVEFORM OF READ CYCLE NO. 1(1)

ADDRESS

OE

CS

DATA OUT

tRC

tAA

tACS

tCLZ (5)

tOE

tOLZ (5)

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)

ADDRESS

DATAOUT

tRC

tAA

tOH

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

COMMERCIAL TEMPERATURE RANGE

tOH

tOHZ (5)

tCHZ (5)

2703 drw 07

t OH

DATA VALID

2703 drw 08

CS

DATAOUT

tCLZ (5)

tACS

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected. CS = VIL.

3. Address valid prior to or coincident with CS transition LOW.

4. OE = VIL.

5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.

tCHZ (5)

2703 drw 06

15.2

5

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