1-Gbit P30 Family
4.0
Ballout and Signal Descriptions
4.1
Signal Ballout
Figure 7. 56-Lead TSOP Pinout (64/128/256-Mbit)
A 16
1
56
A15
2
55
A14
3
54
A13
4
53
A12
5
52
A11
6
51
A10
7
50
A9
8
49
A23
9
48
A22
10
47
A21
11
VSS
12
VCC
13
Intel StrataFlash®
Embedded Memory (P 30)
46
45
44
WE#
14
WP#
15
A20
16
56-Lead TSOP Pinout
14 mm x 20 mm
43
42
41
A19
17
A18
18
Top View
40
39
A8
19
38
A7
20
37
A6
21
36
A5
22
35
A4
23
34
A3
24
33
A2
25
32
A24
26
31
RFU
27
30
VSS
28
29
Notes:
1.
A1 is the least significant address bit.
2.
A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).
3.
A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).
WAIT
A 17
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
ADV#
CLK
RST#
VPP
DQ11
DQ3
DQ10
DQ2
VCCQ
DQ9
DQ1
DQ8
DQ0
VCC
OE #
VSS
CE#
A1
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
17