V437316S04V 데이터 시트보기 (PDF) - Mosel Vitelic, Corp
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V437316S04V Datasheet PDF : 12 Pages
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MOSEL VITELIC
V437316S04V
SPD-Table
Byte Num-
ber
Function Described
28
Minimum Row Active to Row Active Delay
tRRD
29
Minimum RAS to CAS Delay tRCD
30
Minimum RAS Pulse Width tRAS
31
Module Bank Density (Per Bank)
32
SDRAM Input Setup Time
33
SDRAM Input Hold Time
34
SDRAM Data Input Setup Time
35
SDRAM Data Input Hold Time
36-61
Superset Information (May be used in Fu-
ture)
62
SPD Revision
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
65-71
Manufacturer’s JEDEC ID Code (cont.)
72
Manufacturing Location
73-90
Module Part Number (ASCII)
91-92
PCB Identification Code
93
Assembly Manufacturing Date (Year)
94
Assembly Manufacturing Date (Week)
95-98
Assembly Serial Number
99-125 Reserved
126
Intel Specification for Frequency
127
Reserved
128+
Unused Storage Location
SPD Entry Value
15 ns
20 ns
45 ns
128 MByte
1.5 ns
0.8 ns
1.5 ns
0.8 ns
Revision 2
Mosel Vitelic
V437316S04V
DC Characteristics
TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V
Symbol Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
Output High Voltage (IOUT = –2.0 mA)
VOL
Output Low Voltage (IOUT = 2.0 mA)
-75PC
0E
Hex Value
-75
0F
0F
14
2A
2D
20
20
15
15
08
08
15
15
08
08
00
00
02
02
EC
31
40
40
00
00
00
00
64
64
00
00
00
00
Limit Values
Min.
Max.
2.0
–0.5
VCC+0.3
0.8
2.4
—
—
0.4
-10PC
10
14
2D
20
20
10
20
10
00
02
8F
40
00
00
64
00
00
Unit
V
V
V
V
V437316S04V Rev. 1.0 December 2001
5
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