CB35000 데이터 시트보기 (PDF) - STMicroelectronics

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CB35000

HCMOS STANDARD CELLS

STMicroelectronics 

Figure 8

SGS-THOMSON Design Flow

HARDWARE DESCRIPTION

LANGUAGE

VHDL / HDL

LOGIC SYNTHESIS

SYNOPSYS

GATE LEVEL SIMULATION

VERILOG-XL

MENTOR

SYSTEM HILO

VSS

TSSI

CURRENTEST

SIGN OFF SIMULATION

SGS-THOMSON

CB35000 SERIES

FUNCTIONAL

SIMULATION

VHDL / HDL

SCHEMATIC CAPTURE

CADENCE

MENTOR

FLOORPLANNING

DELAY EVALUATION

RC BACK ANNOTATION

CLOCK TREE SYNTHESIS

LAYOUT

SILICON

11/16

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