HFA3841 데이터 시트보기 (PDF) - Intersil

부품명

상세내역

일치하는 목록

HFA3841

Wireless LAN Medium Access Controller

Intersil 

Waveforms

OSC

MCLK

(INTERNAL)

Preliminary - HFA3841

tH1

tH1

tD1

tCYC

FIGURE 1. CLOCK SIGNAL TIMING

OSC

MCLK

(INTERNAL)

QCLK

(INTERNAL)

MCLKOUT

ADDRESS,

RAMCS_

MOE_

44MHz

23ns

10ns (NOTE 10)

11MHz

91ns

11.5ns

17ns

MD0-15

READ DATA

MWEH/L_

23ns

17ns

24ns

VALID DATA AT MDIN

tH≥0

13ns

16ns

MD0-15,

WRITE DATA

MBUS READ CYCLE

VALID DATA

20ns

MBUS WRITE CYCLE

NOTE:

10. Timing delays between OSC and internal clocks are shown for information purposes only.

FIGURE 2. MBUS MEMORY TIMING - 11MHz MCLK

tH≥0

10

Share Link: