W210H 데이터 시트보기 (PDF) - Cypress Semiconductor
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W210H Datasheet PDF : 14 Pages
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W210
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF
Parameter
Description
Test Condition/Comments
tP
Period
Measured on rising edge at 1.5V
tH
High Time
Duration of clock cycle above 2.4V
tL
Low Time
Duration of clock cycle below 0.4V
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
tF
Output Fall Edge Rate Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
tSK
Output Skew
Measured on rising edge at 1.5V
tO
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold
from power-up. Short cycles exist prior to frequency
start)
stabilization.
Zo
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
Min.
30
12
12
1
1
45
1.5
Typ.
30
Max.
4
4
55
250
500
4
3
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Ω
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization from Assumes full supply voltage reached within
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
Typ.
14.318
40
Max.
2
2
55
3
Unit
MHz
V/ns
V/ns
%
ms
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
fD
Deviation from 48 MHz
(48.008 – 48)/48
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
quency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
Typ.
48.008
+167
57/17
40
Max.
2
2
55
3
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
11
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