5962R9582001QJC 데이터 시트보기 (PDF) - Intersil

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5962R9582001QJC

Radiation Hardened CMOS Static Clock Controller/Generator

Intersil 

Waveforms (Continued)

EFI OR OSC

PCLK

SLO/FST

CLK

HS-82C85RH

tSFPC

(NOTE)

tSFPC (NOTE)

3 EFI PULSES

CLK50

FIGURE 11. SLOW TO FAST CLOCK MODE TRANSITION

NOTE: If tSFPC is not met on one edge of PCLK, SLO/FST will be recognized on the next edge of PCLK.

X1

15MHz

C1

X2

C2

CLK

CLK50

LOAD †

LOAD †

F/C

CSYNC

FIGURE 12. CLOCK HIGH AND LOW TIME (USING X1, X2)

PULSE

GENERATOR

EFI

CLK

LOAD †

VDD

F/C

CLK50

LOAD †

CSYNC

FIGURE 13. CLOCK HIGH AND LOW TIME (USING EFI)

VDD

AEN1

CLK

X1

C1

15MHz

TRIGGER

PULSE

GENERATOR

X2

C2

READY

RDY2

F/C

AEN2

CSYNC

OSC

LOAD †

LOAD †

FIGURE 14. READY TO CLOCK (USING X1, X2)

† CL = 50pF

9

PULSE

GENERATOR

TRIGGER

PULSE

GENERATOR

VDD

EFI

F/C

AEN1

CLK

RDY2

AEN2

CSYNC

READY

LOAD †

LOAD †

FIGURE 15. READY TO CLOCK (USING EFI)

FN3044.3

April 20, 2007

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