CD4034BMS 데이터 시트보기 (PDF) - Intersil
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CD4034BMS Datasheet PDF : 14 Pages
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CD4034BMS
VSS
PROTECTION NETWORK
ON ALL “A” AND “B”
DATA INPUTS
K
p
n
K
P/S
CLM
An
CLS
1 OF 8 STAGES
M
Q’
Q’
VDD
SERIAL
DATA
VDD
D
p
n
P/S
p
n
CLM
CLM
p
n
p
n
CLS
CLS
p
n
L CLM
CLS
VSS
PROTECTION NETWORK
ON SERIAL DATA INPUT
p
n
L
Bn
FIGURE 11. REGISTER STAGE LOGIC DIAGRAM (1 OF 8 STAGES)
M
VSS
N
VDD
Q’
N
VSS
Q (TO NEXT STAGE D)
TRUTH TABLE REGISTER INPUT-LEVELS AND
RESULTING REGISTER OPERATION
“A”
ENABLE P/S
A/B
A/S
OPERATION*
0
0
0
X
Serial Mode; Synch. Serial Data Input, “A” Parallel Data Outputs Disabled
0
0
1
X
Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output
0
1
0
0
Parallel Mode; “B” Synch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled
0
1
0
1
Parallel Mode; “B” Asynch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled
0
1
1
0
Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Synch. Data
Recirculation
0
1
1
1
Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Asynch. Data
Recirculation
1
0
0
X
Serial Mode; Synch. Serial Data Input, “A” Parallel Data Output
1
0
1
X
Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output
1
1
0
0
Parallel Mode; “B” Synch. Parallel Data Input, “A” Parallel Data Output
1
1
0
1
Parallel Mode; “B” Asynch. Parallel Data Input, “A” Parallel Data Output
1
1
1
0
Parallel Mode; “A” Synch, Parallel Data Input, “B” Parallel Data Output
1
1
1
1
Parallel Mode; “A” Asynch. Parallel Data Input, “B” Parallel Data Output
*Outputs change at positive transition of clock in the serial mode and when the A/S control input is “low” in the parallel mode. During
transfer from parallel to serial operation A/S should remain low in order to prevent DS transfer into Flip Flops.
1 = High Level
0 = Low Level
X = Don’t Care
7-847
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