HD404326UFS 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HD404326UFS

4-Bit Microcontroller

Hitachi -> Renesas Electronics 

HD404328 Series

Bit 3

IM0

0

(IM of INT0)

IMTA

1

(IM of timer A)

IMTC

2 (IM of timer C)

IMAD

3

(IM of A/D)

Bit 2

IF0

(IF of INT0)

IFTA

(IF of timer A)

IFTC

(IF of timer C)

IFAD

(IF of A/D)

Bit 1

RSP

(Reset SP bit)

IM1

(IM of INT1)

IMTB

(IM of timer B)

IMZC

(IM of ZCD)

Bit 0

IE

(Interrupt enable flag) $000

IF1

(IF of INT1)

IFTB

(IF of timer B)

$001

$002

IFZC

(IF of ZCD)

$003

32

DTON

(Direct transfer

on

flag)

ADSF

(A/D start flag)

WDON

(Watchdog on flag)

LSON

(Low speed on flag)

$020

33

$021

Not used

34

$022

35

IMS

(IM of serial interface)

IFS

(IF of serial interface)

$023

IF: Interrupt request flag

IM: Interrupt mask

IE: Interrupt enable flag

SP: Stack pointer

Note: Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD instruction,

reset by the REM or REMD instruction, and tested by the TM or TMD instruction. Other

instructions have no effect.

However, note the following usage limitations of RAM bit manipulation instructions.

IF

RSP

WDON

DTON

SEM/SEMD

Not executed

Not executed

Allowed

Not executed in active mode

Used in subactive mode

REM/REMD

Allowed

Allowed

Not executed

Allowed

TM/TMD

Allowed

Inhibited

Inhibited

Allowed

Note: WDON is reset by MCU reset.

DTON is always reset in active mode.

If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,

the value in ST becomes invalid.

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

11

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