ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCHÎÎÎÎARÎÎÎÎAChCaÎÎÎÎTrEacRtÎÎÎÎeISriTsÎÎÎÎtIiCcSÎÎÎÎ* (CÎÎÎÎL=5ÎÎÎÎ0pFÎÎÎÎ,TAÎÎÎÎ=2ÎÎÎÎ5_CÎÎÎÎ)SymÎÎÎÎbolÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎTÎÎÎÎypÎÎÎÎ# ÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎUÎÎÎÎnitÎÎÎÎ
Output Rise and Fall Time
tTLH, tTHL = (1.6 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
ns
tTHL
5.0
—
100
200
10
—
50
100
15
—
40
80
Propagation Delay Time
Data to Q
tPLH, tPHL = (1.7 ns/pF) CL + 355 ns
tPLH, tPHL = (0.66 ns/pF) CL + 142 ns
tPLH, tPHL = (0.5 ns/pF) CL + 95 ns
Odd/Even to Q
tPLH, tPHL = (1.7 ns/pF) CL + 165 ns
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns
tPLH, tPHL = (0.5 ns/pF) CL + 45 ns
tPLH,
ns
tPHL
5.0
—
440
1320
10
—
175
525
15
—
120
360
5.0
—
250
750
10
—
100
300
15
—
70
210
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
20 ns
90%
VDD
SIGNAL
10%
50%
INPUT
VSS
1
DATA RATE (f)
f IN RESPECT TO SYSTEM CLOCK
Figure 1. Dynamic Power Dissipation
Signal Waveform
INPUT
(D OR W) tPLH
10%
OUTPUT
20 ns
90%
50%
90%
tTLH
20 ns
VDD
10% VSS
tPHL
VOH
50%
VOL
tTHL
Figure 2. Dynamic Signal Waveforms
MOTOROLA CMOS LOGIC DATA
MC14531B
3