DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
TEST CIRCUITS
MC54/74HCT373A
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 5.
* Includes all probe and jig capacitance
Figure 6.
High–Speed CMOS Logic Data
5
DL129 — Rev 6
MOTOROLA