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74F109 데이터시트 - Fairchild Semiconductor

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74F109 Dual JK Positive Edge-Triggered Flip-Flop Fairchild
Fairchild Semiconductor Fairchild
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74F109 데이타시트 PDF : 74F109 pdf   
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General Description
The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs.

Asynchronous Inputs:
   LOW input to SD sets Q to HIGH level
   LOW input to CD sets Q to LOW level
   Clear and Set are independent of clock
   Simultaneous LOW on CD and SD makes
      both Q and Q HIGH

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"74F109" 관련 부품명

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