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S16008LK7 Datasheet PDF - ETC1

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General Description:
The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. Each is internally configured as a quad-bank DRAM. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

• Intel PC-100 (3-3-3) or PC133 (3-3-3) compatible
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access precharge time
• Programmable burst lengths: 1, 2, or 4 using Interleaved Burst Addressing
• Auto Precharge and Auto Refresh modes
• 64ms, 4,096-cycle refresh quad-row refresh, (15.6ms/row)
• Self Refresh mode 1
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• The x16 devices are optimized for both single and dual rank DIMM applications. The x8 devices are optimized for single rank DIMM applications.


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